| LC control no. | sh2003001198 |
|---|---|
| Topical heading | Itanium (Microprocessor) |
| See also | Intel microprocessors RISC microprocessors |
| Found in | Work cat.: Evans, James S. Itanium architecture for programmers, c2003: CIP t.p. (Itanium microprocessor; successor to the Pentium microprocessor) Webopedia, Jan. 6, 2003 (A member of Intel's new Merced family of processors, Itanium is a 64-bit RISC microprocessor. Based on the EPIC (Explicitly Parallel Instruction Computing) design philosophy, which states that the compiler should decide which instructions be executed together, Itanium has the highest FPU power available. In 64-bit mode, Itanium is able to calculate two bundles of a maximum of three instructions at a time. In 32-bit mode, it is much slower. Decoders must first translate 32-bit instruction sets into 64-bit instruction sets, which results in extra-clock cycle use. Itanium's primary use is driving large applications that require more than 4 GB of memory, such as databases, ERP, and future Internet applications) Microsoft computer dict., 5th ed., c2002 (An Intel microprocessor that uses explicitly parallel instruction set computing and 64-bit memory addressing) |
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